Recent questions tagged verilog

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?

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1.5k views 1 answer

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - What is `+:` and `-:`?

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1.1k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - I don't understand this define macro with replication

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1.3k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - $fgetc SystemVerilog function doesn't read from stdin

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1.3k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Why are "if..else" statements not encouraged within systemverilog assertion property?

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1.4k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - For loop with binary numbers

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1.3k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - 4 bit register with enable and asynchronous reset

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1.3k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Arbitrary Counter only displaying zeros

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1.1k views 1 answer

asked Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

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1.4k views 1 answer

asked Feb 21, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

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1.4k views 1 answer

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Writing random data to a RAM in a testbench

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1.6k views 1 answer

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Passing packed data to a task to be compared with an unpacked data array for uvm constraints

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1.7k views 1 answer

asked Feb 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Parameterizing a SystemVerilog interface for optional array of a port element

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1.7k views 1 answer

asked Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Functional Coverage - bin that collects all values that are not collected in other bins

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3.2k views 1 answer

asked Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Functional Coverage - bin that collects all values that are not collected in other bins

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3.5k views 1 answer

asked Jan 25, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - How can I automatically scale a $display column width?

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4.2k views 1 answer

asked Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Does this SystemVerilog code have the wrong sequence of code?

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4.3k views 1 answer

asked Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

verilog - Does this SystemVerilog code have the wrong sequence of code?

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4.4k views 1 answer

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